Drafting and enforcing semiconductor patents

By Doris Johnson Hines

Semiconductor patents, those that protect the invention of new computer memory chips, are among the most commonly granted modern patents.

Protecting semiconductor device and fabrication process inventions can be challenging. This is because showing that these types of inventions are being used by others often requires reverse engineering, a process that is costly and time consuming and that may not even show that an invention is being used. Patent drafters who do not fully understand the underlying technology and the limits of reverse engineering can thus make enforcement and licensing of valuable semiconductor IP very difficult. We discuss below several issues relating to semiconductor patent enforcement and licensing, and several factors to consider when drafting semiconductor patent applications with an eye towards enforcement and licensing. 

To show infringement, a patent owner needs to show that an accused product or process meets each element of a patent claim. For example, if a semiconductor device claim recites: “a metal-oxide-semiconductor device including: a source; a drain; and a gate structure,” to show infringement, the accused product must include a device made of metal, oxide, and semiconductor, and must also include a source, a drain, and a gate structure. 

The nature of semiconductor devices presents challenges because such devices are manufactured in nanometer scale, and often built in a multilayer structure, making any analysis of infringing products time-consuming and costly. Showing infringement of a nanoscale, multilayer semiconductor device including a gate structure may require multiple high-resolution cross-sectional scanning electron microscope (SEM) and transmission electron microscope (TEM) analyses. In addition, multiple metal layers from the back end of line (BEOL) process may have to be removed by etching processes if a plan view of the gate structure is required. 

Additionally, claimed features may require increased time and cost in the reverse engineering process. Assume that the previous claim example is modified and the claim recites “a polysilicon gate structure having a phosphorus doping concentration of 1E20/cm3,” instead of simply “a gate structure.” In addition to SEM, TEM, and etching processes, other analyses may be necessary, such as energy dispersive xray spectroscopy (EDS) and secondary ion mass spectrometry (SIMS). The cost of these reverse engineering analyses can be tens of thousands of dollars (or more), depending what the claim recites. 

The time and cost of demonstrating patent infringement can be exacerbated by claims that are unnecessarily specific or unclear, sometimes the result of a patent drafter unfamiliar with the technology. Further, oftentimes a patent owner will need to analyze a large portfolio of devices to identify infringing products. All of the above may make a patent supposedly protecting a critical invention very difficult to enforce or to explain in license negotiations. Furthermore, reasonable pre-suit investigation of infringement is required, meaning that costly reverse engineering may be necessary before an enforcement action can be brought. Thus, reverse engineering potentially infringing products is often a necessary step of enforcing a semiconductor patent. 

To mitigate the challenges and costs discussed above, semiconductor patent applications and claims should be drafted by practitioners familiar with the technology and who are more likely to understand whether certain features can be easily identified in infringing products. Furthermore, a knowledgeable drafter will be able to write patent claims that best protect the invention without being overly difficult to demonstrate. 

A couple of factors affecting the identification of claim features using reverse engineering, often overlooked, should be considered when drafting claims. First, when drafting a semiconductor process claim, one should pay additional attention to subtractive steps in a semiconductor fabrication process, e.g., an etching process. For example, if a process claim recites: “isotropically etching the second layer,” it may not be straightforward to show, by just analyzing the finished product, whether an isotropic etching process was performed to remove the second layer (infringement) or the second layer never even existed (non-infringement). This type of claim element makes it difficult to prove if the claimed process is used in manufacturing of potentially infringing products.  A claim element easily identifiable via reverse engineering is critical because detailed steps in semiconductor fabrication processes are likely not published and are often protected trade secrets. 

Second, the analytical capabilities of the tools used for reverse engineering (such as spectroscopy and electron microscope) have limits. These limits often determine which feature can be identified through reverse engineering in an accused product, which may, in turn, determine what features should be included in a claim. Intuitively, qualitative analysis (e.g., existence of a certain phosphorus in a semiconductor layer) is less challenging than quantitative analysis (e.g., a certain concentration of phosphorus). A patent drafter should understand the analytical limits of reverse engineering techniques to draft and prosecute patent claims that cover the invention well and also can be shown with those reverse engineering techniques. 

There are unique challenges to drafting and enforcing semiconductor patents because of the semiconductor devices’ miniature nature, complicated fabrication processes, and the necessity of highly-technical and expensive reverse-engineering analyses to show infringement. Semiconductor patent applications should be drafted with these considerations in mind.

About the author

Doris Johnson Hines
Doris Hines focuses her practice on patent litigation, leading teams in U.S. district courts, the U.S. International Trade Commission (ITC), and before arbitration panels. Dori regularly represents clients in mediations and assists in licensing negotiations. She advises clients on strategic patent prosecution, monetization strategies for issued patents, and patent damages, including issues relating to standard essential patents and fair, reasonable, and non-discriminatory (FRAND) terms. She is reachable at doris.hines[at]finnegan.com.